"FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking."

Jinsong Bei et al. (1999)

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DOI: 10.1109/ASPDAC.1999.760034

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong:
FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. ASP-DAC 1999: 363-

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