"Specification and verification of gate-level VHDL models of synchronous ..."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

David M. Russinoff (1993)

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type: Part in Book or Collection

metadata version: 2017-11-20

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David M. Russinoff:
Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits. Specification and validation methods 1993: 411-460

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