"A test pattern selection method for dynamic burn-in of logic circuits ..."

Xuan Yang et al. (2013)

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DOI: 10.1109/ASICON.2013.6811958

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-07

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Xuan Yang, Xiaole Cui, Chao Wang, Chung Len Lee:
A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique. ASICON 2013: 1-4

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