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"A Low-delay Configurable Register for FPGA."

Zhi-Yin Lu et al. (2019)

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DOI: 10.1109/ASICON47005.2019.8983553

access: closed

type: Conference or Workshop Paper

metadata version: 2022-06-15

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  dblp key:
  - conf/asicon/LuLPLZLW19
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  - https://dblp.org/rec/conf/asicon/LuLPLZLW19
Zhi-Yin Lu, Jia-Feng Liu, Yunbing Pang, Zhengjie Li, Yufan Zhang, Jin-Mei Lai, Jian Wang:
A Low-delay Configurable Register for FPGA. ASICON 2019: 1-4

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