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"Variation Analysis of Interconnect Capacitance and Process Corner in ..."

Zhimei Cai et al. (2019)

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DOI: 10.1109/ASICON47005.2019.8983474

access: closed

type: Conference or Workshop Paper

metadata version: 2020-02-12

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  - conf/asicon/CaiHTWHCZ19
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  - https://dblp.org/rec/conf/asicon/CaiHTWHCZ19
Zhimei Cai, Zhiyong Han, Ming Tian, Changfeng Wang, Xiaoming Hu, Ran Cheng, Yi Zhao:
Variation Analysis of Interconnect Capacitance and Process Corner in Advanced CMOS Process with Double Patterning Technology. ASICON 2019: 1-4

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