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"SHA-3 Instruction Set Extension for A 32-bit RISC processor architecture."

Ahmed S. Eissa et al. (2016)

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DOI: 10.1109/ASAP.2016.7760804

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/asap/EissaESAF16
Ahmed S. Eissa, Mahmoud A. Elmohr, Mostafa A. Saleh, Khaled E. Ahmed, Mohammed M. Farag:
SHA-3 Instruction Set Extension for A 32-bit RISC processor architecture. ASAP 2016: 233-234

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