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"An FPGA run-time parameterisable Log-Normal Random Number Generator."

Pedro Echeverría et al. (2008)

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DOI: 10.1007/978-3-540-78610-8_22

access: closed

type: Conference or Workshop Paper

metadata version: 2021-04-09

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  dblp key:
  - conf/arc/EcheverriaTLL08
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  - https://dblp.org/rec/conf/arc/EcheverriaTLL08
Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk:
An FPGA run-time parameterisable Log-Normal Random Number Generator. ARC 2008: 219-230

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