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"Stacked Active Loads For Low Power, High Speed GaAs Digital Circuits (SALFL)."

A. K. Mrunal, M. A. Shirasgaonkar, Rajendra M. Patrikar (2006)

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DOI: 10.1109/APCCAS.2006.342504

access: closed

type: Conference or Workshop Paper

metadata version: 2020-08-13

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  dblp key:
  - conf/apccas/MrunalSP06a
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  - https://dblp.org/rec/conf/apccas/MrunalSP06a
A. K. Mrunal, M. A. Shirasgaonkar, Rajendra M. Patrikar:
Stacked Active Loads For Low Power, High Speed GaAs Digital Circuits (SALFL). APCCAS 2006: 1488-1491

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