"Impact of skew and jitter on the performance of VLSI interconnects."

Gargi Khanna, Rajeevan Chandel, Ashwani Kumar Chandel (2010)

Details and statistics

DOI: 10.1109/APCCAS.2010.5775007

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

a service of  Schloss Dagstuhl - Leibniz Center for Informatics