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"Application of a redefinable symbolic simulation technique in VLSI ..."

Mokhtar Hirech et al. (1994)

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DOI: 10.1109/SIMSYM.1994.283090

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/anss/HirechFGR94
Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan:
Application of a redefinable symbolic simulation technique in VLSI testability design rules checking. Annual Simulation Symposium 1994: 255-261

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