"An hardware accelerator design of Mobile-Net model on FPGA."

Sanjaya M. V, Madhav Rao (2022)

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DOI: 10.1145/3564121.3564124

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

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Sanjaya M. V, Madhav Rao:
An hardware accelerator design of Mobile-Net model on FPGA. AIMLSystems 2022: 2:1-2:9

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