"A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction ..."

Ciaran Toal, Sakir Sezer (2005)

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DOI: 10.1109/AICT.2005.1

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Ciaran Toal, Sakir Sezer:
A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA. AICT/SAPIR/ELETE 2005: 357-362

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