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"Simulation of large asynchronous logic circuits using an ambiguous gate model."

Stephen G. Chappell, Stephen S. Yau (1971)

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DOI: 10.1145/1479064.1479176

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - conf/afips/ChappellY71
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  - https://dblp.org/rec/conf/afips/ChappellY71
Stephen G. Chappell, Stephen S. Yau:
Simulation of large asynchronous logic circuits using an ambiguous gate model. AFIPS Fall Joint Computing Conference 1971: 651-661

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