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"FPGA-accelerated simulation of truncated-matrix multipliers."

E. George Walters III (2012)

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DOI: 10.1109/ACSSC.2012.6489166

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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E. George Walters III:
FPGA-accelerated simulation of truncated-matrix multipliers. ACSCC 2012: 993-997

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