BibTeX record journals/tvlsi/SongWHLCL17

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@article{DBLP:journals/tvlsi/SongWHLCL17,
  author    = {Lili Song and
               Ying Wang and
               Yinhe Han and
               Huawei Li and
               Yuanqing Cheng and
               Xiaowei Li},
  title     = {{STT-RAM} Buffer Design for Precision-Tunable General-Purpose Neural
               Network Accelerator},
  journal   = {{IEEE} Trans. {VLSI} Syst.},
  volume    = {25},
  number    = {4},
  pages     = {1285--1296},
  year      = {2017},
  url       = {https://doi.org/10.1109/TVLSI.2016.2644279},
  doi       = {10.1109/TVLSI.2016.2644279},
  timestamp = {Thu, 21 Sep 2017 12:05:02 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tvlsi/SongWHLCL17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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