BibTeX record journals/tvlsi/NdaiGR10

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@article{DBLP:journals/tvlsi/NdaiGR10,
  author    = {Patrick Ndai and
               Ashish Goel and
               Kaushik Roy},
  title     = {A Scalable Circuit-Architecture Co-Design to Improve Memory Yield
               for High-Performance Processors},
  journal   = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume    = {18},
  number    = {8},
  pages     = {1209--1219},
  year      = {2010},
  url       = {https://doi.org/10.1109/TVLSI.2009.2022628},
  doi       = {10.1109/TVLSI.2009.2022628},
  timestamp = {Wed, 11 Mar 2020 18:18:43 +0100},
  biburl    = {https://dblp.org/rec/journals/tvlsi/NdaiGR10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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