BibTeX record journals/tvlsi/NdaiGR10

download as .bib file

@article{DBLP:journals/tvlsi/NdaiGR10,
  author    = {Patrick Ndai and
               Ashish Goel and
               Kaushik Roy},
  title     = {A Scalable Circuit-Architecture Co-Design to Improve Memory Yield
               for High-Performance Processors},
  journal   = {{IEEE} Trans. {VLSI} Syst.},
  volume    = {18},
  number    = {8},
  pages     = {1209--1219},
  year      = {2010},
  url       = {https://doi.org/10.1109/TVLSI.2009.2022628},
  doi       = {10.1109/TVLSI.2009.2022628},
  timestamp = {Thu, 18 May 2017 09:50:47 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tvlsi/NdaiGR10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
maintained by Schloss Dagstuhl LZI at University of Trier