BibTeX record journals/tcas/WenCZTZ16

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@article{DBLP:journals/tcas/WenCZTZ16,
  author       = {Liang Wen and
                  Xu Cheng and
                  Keji Zhou and
                  Shudong Tian and
                  Xiaoyang Zeng},
  title        = {Bit-Interleaving-Enabled 8T {SRAM} With Shared Data-Aware Write and
                  Reference-Based Sense Amplifier},
  journal      = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
  volume       = {63-II},
  number       = {7},
  pages        = {643--647},
  year         = {2016},
  url          = {https://doi.org/10.1109/TCSII.2016.2530881},
  doi          = {10.1109/TCSII.2016.2530881},
  timestamp    = {Fri, 09 Apr 2021 18:23:18 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/WenCZTZ16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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