BibTeX record conf/vlsid/ThakkarP17

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@inproceedings{DBLP:conf/vlsid/ThakkarP17,
  author       = {Ishan G. Thakkar and
                  Sudeep Pasricha},
  title        = {DyPhase: {A} Dynamic Phase Change Memory Architecture with Symmetric
                  Write Latency},
  booktitle    = {30th International Conference on {VLSI} Design and 16th International
                  Conference on Embedded Systems, {VLSID} 2017, Hyderabad, India, January
                  7-11, 2017},
  pages        = {41--46},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/VLSID.2017.6},
  doi          = {10.1109/VLSID.2017.6},
  timestamp    = {Fri, 24 Mar 2023 00:03:59 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/ThakkarP17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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