BibTeX record conf/vlsid/PhanseS01

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@inproceedings{DBLP:conf/vlsid/PhanseS01,
  author    = {Siddharth R. Phanse and
               R. K. Shyamasundar},
  title     = {Application of Esterel for Modelling and Verification of Cachet Protocol
               on {CRF} Memory Model},
  booktitle = {14th International Conference on {VLSI} Design {(VLSI} Design 2001),
               3-7 January 2001, Bangalore, India},
  pages     = {179--188},
  year      = {2001},
  crossref  = {DBLP:conf/vlsid/2001},
  url       = {https://doi.org/10.1109/ICVD.2001.902658},
  doi       = {10.1109/ICVD.2001.902658},
  timestamp = {Tue, 23 May 2017 01:13:11 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsid/PhanseS01},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsid/2001,
  title     = {14th International Conference on {VLSI} Design {(VLSI} Design 2001),
               3-7 January 2001, Bangalore, India},
  publisher = {{IEEE} Computer Society},
  year      = {2001},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7234},
  isbn      = {0-7695-0831-6},
  timestamp = {Mon, 20 Apr 2015 18:26:36 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsid/2001},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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