BibTeX record conf/vlsid/PaliwalFCG16

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@inproceedings{DBLP:conf/vlsid/PaliwalFCG16,
  author       = {Pallavi Paliwal and
                  Jaydip Fadadu and
                  Anil Chawda and
                  Shalabh Gupta},
  title        = {A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop},
  booktitle    = {29th International Conference on {VLSI} Design and 15th International
                  Conference on Embedded Systems, {VLSID} 2016, Kolkata, India, January
                  4-8, 2016},
  pages        = {553--554},
  publisher    = {{IEEE} Computer Society},
  year         = {2016},
  url          = {https://doi.org/10.1109/VLSID.2016.48},
  doi          = {10.1109/VLSID.2016.48},
  timestamp    = {Fri, 24 Mar 2023 00:03:59 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/PaliwalFCG16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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