BibTeX record conf/vlsid/BalajiCT08

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@inproceedings{DBLP:conf/vlsid/BalajiCT08,
  author       = {Balaji Srinivasan and
                  Vinay Bhaskar Chandratre and
                  Menka Tewani},
  title        = {0.35{\(\mathrm{\mu}\)}, 1 GHz, {CMOS} Timing Generator Using Array
                  of Digital Delay Lock Loops},
  booktitle    = {21st International Conference on {VLSI} Design {(VLSI} Design 2008),
                  4-8 January 2008, Hyderabad, India},
  pages        = {613--619},
  publisher    = {{IEEE} Computer Society},
  year         = {2008},
  url          = {https://doi.org/10.1109/VLSI.2008.95},
  doi          = {10.1109/VLSI.2008.95},
  timestamp    = {Fri, 24 Mar 2023 00:04:01 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/BalajiCT08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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