BibTeX record conf/vlsic/PatilRMT15

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@inproceedings{DBLP:conf/vlsic/PatilRMT15,
  author    = {Sharvil Patil and
               Alin Ratiu and
               Dominique Morche and
               Yannis P. Tsividis},
  title     = {A 3-10fJ/conv-step 0.0032mm\({}^{\mbox{2}}\) error-shaping alias-free
               asynchronous {ADC}},
  booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2015, Kyoto, Japan, June 17-19,
               2015},
  pages     = {160},
  year      = {2015},
  crossref  = {DBLP:conf/vlsic/2015},
  url       = {https://doi.org/10.1109/VLSIC.2015.7231249},
  doi       = {10.1109/VLSIC.2015.7231249},
  timestamp = {Sun, 21 May 2017 00:21:39 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsic/PatilRMT15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsic/2015,
  title     = {Symposium on {VLSI} Circuits, {VLSIC} 2015, Kyoto, Japan, June 17-19,
               2015},
  publisher = {{IEEE}},
  year      = {2015},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7196579},
  isbn      = {978-4-86348-502-0},
  timestamp = {Wed, 16 Mar 2016 13:17:20 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/vlsic/2015},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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