BibTeX record conf/vlsic/MathewSSKACAHK14

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@inproceedings{DBLP:conf/vlsic/MathewSSKACAHK14,
  author       = {Sanu Mathew and
                  Sudhir Satpathy and
                  Vikram B. Suresh and
                  Himanshu Kaul and
                  Mark A. Anders and
                  Gregory K. Chen and
                  Amit Agarwal and
                  Steven Hsu and
                  Ram Krishnamurthy},
  title        = {340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with
                  area-optimized encrypt/decrypt GF(2\({}^{\mbox{4}}\))\({}^{\mbox{2}}\)
                  polynomials in 22nm tri-gate {CMOS}},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2014, Digest of Technical Papers,
                  Honolulu, HI, USA, June 10-13, 2014},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/VLSIC.2014.6858420},
  doi          = {10.1109/VLSIC.2014.6858420},
  timestamp    = {Fri, 25 Feb 2022 16:33:50 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsic/MathewSSKACAHK14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}