BibTeX record conf/vlsic/LuoCSWSLLLLLCSK15

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@inproceedings{DBLP:conf/vlsic/LuoCSWSLLLLLCSK15,
  author       = {Pei{-}Wen Luo and
                  Chi{-}Kang Chen and
                  Yu{-}Hui Sung and
                  Wei Wu and
                  Hsiu{-}Chuan Shih and
                  Chia{-}Hsin Lee and
                  Kuo{-}Hua Lee and
                  Ming{-}Wei Li and
                  Mei{-}Chiang Lung and
                  Chun{-}Nan Lu and
                  Yung{-}Fa Chou and
                  Po{-}Lin Shih and
                  Chung{-}Hu Ke and
                  Chun Shiah and
                  Patrick Stolt and
                  Shigeki Tomishima and
                  Ding{-}Ming Kwai and
                  Bor{-}Doou Rong and
                  Nicky Lu and
                  Shih{-}Lien Lu and
                  Cheng{-}Wen Wu},
  title        = {A computer designed half Gb 16-channel 819Gb/s high-bandwidth and
                  10ns low-latency {DRAM} for 3D stacked memory devices using TSVs},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2015, Kyoto, Japan, June 17-19,
                  2015},
  pages        = {186},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSIC.2015.7231256},
  doi          = {10.1109/VLSIC.2015.7231256},
  timestamp    = {Sat, 30 Sep 2023 09:58:21 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/LuoCSWSLLLLLCSK15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}