BibTeX record conf/vlsic/BhavnagarwalaIN16

• > Home > conf/vlsic/BhavnagarwalaIN16

@inproceedings{DBLP:conf/vlsic/BhavnagarwalaIN16,
  author       = {Azeez Bhavnagarwala and
                  Imran Iqbal and
                  An Nguyen and
                  David Ondricek and
                  Vikas Chandra and
                  Robert C. Aitken},
  title        = {A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb {SRAM} with
                  a 0.09 um\({}^{\mbox{2}}\) 6T bitcell in a 16nm FinFET {CMOS} process},
  booktitle    = {2016 {IEEE} Symposium on {VLSI} Circuits, {VLSIC} 2016, Honolulu,
                  HI, USA, June 15-17, 2016},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/VLSIC.2016.7573513},
  doi          = {10.1109/VLSIC.2016.7573513},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/BhavnagarwalaIN16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}