BibTeX record conf/vlsi/ShresthaS18

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@inproceedings{DBLP:conf/vlsi/ShresthaS18,
  author       = {Rahul Shrestha and
                  Ashutosh Sharma},
  title        = {VLSI-Architecture of Radix-2/4/8 {SISO} Decoder for Turbo Decoding
                  at Multiple Data-rates},
  booktitle    = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
  pages        = {131--136},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/VLSI-SoC.2018.8644753},
  doi          = {10.1109/VLSI-SOC.2018.8644753},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/ShresthaS18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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