BibTeX record conf/vlsi/RakossySALC15

• > Home > conf/vlsi/RakossySALC15

@inproceedings{DBLP:conf/vlsi/RakossySALC15,
  author       = {Zolt{\'{a}}n Endre R{\'{a}}kossy and
                  Dominik Stengele and
                  Gerd Ascheid and
                  Rainer Leupers and
                  Anupam Chattopadhyay},
  title        = {Exploiting scalable {CGRA} mapping of {LU} for energy efficiency using
                  the Layers architecture},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {337--342},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314440},
  doi          = {10.1109/VLSI-SOC.2015.7314440},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/RakossySALC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}