BibTeX record conf/vldb/ArefyevaDPBS18

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@inproceedings{DBLP:conf/vldb/ArefyevaDPBS18,
  author    = {Iya Arefyeva and
               Gabriel Campero Durand and
               Marcus Pinnecke and
               David Broneske and
               Gunter Saake},
  title     = {Low-Latency Transaction Execution on Graphics Processors: Dream or
               Reality?},
  booktitle = {International Workshop on Accelerating Analytics and Data Management
               Systems Using Modern Processor and Storage Architectures, ADMS@VLDB
               2018, Rio de Janeiro, Brazil, August 27, 2018.},
  pages     = {16--21},
  year      = {2018},
  crossref  = {DBLP:conf/vldb/2018adms},
  url       = {http://www.adms-conf.org/2018-camera-ready/low-latency.pdf},
  timestamp = {Mon, 01 Oct 2018 14:04:28 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vldb/ArefyevaDPBS18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vldb/2018adms,
  editor    = {Rajesh Bordawekar and
               Tirthankar Lahiri},
  title     = {International Workshop on Accelerating Analytics and Data Management
               Systems Using Modern Processor and Storage Architectures, ADMS@VLDB
               2018, Rio de Janeiro, Brazil, August 27, 2018},
  year      = {2018},
  timestamp = {Mon, 01 Oct 2018 14:04:20 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vldb/2018adms},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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