BibTeX record conf/memocode/PetersPWD16

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@inproceedings{DBLP:conf/memocode/PetersPWD16,
  author    = {Judith Peters and
               Nils Przigoda and
               Robert Wille and
               Rolf Drechsler},
  title     = {Clocks vs. instants relations: Verifying {CCSL} time constraints in
               {UML/MARTE} models},
  booktitle = {2016 {ACM/IEEE} International Conference on Formal Methods and Models
               for System Design, {MEMOCODE} 2016, Kanpur, India, November 18-20,
               2016},
  pages     = {78--84},
  year      = {2016},
  crossref  = {DBLP:conf/memocode/2016},
  url       = {https://doi.org/10.1109/MEMCOD.2016.7797750},
  doi       = {10.1109/MEMCOD.2016.7797750},
  timestamp = {Fri, 02 Nov 2018 09:46:51 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/memocode/PetersPWD16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/memocode/2016,
  title     = {2016 {ACM/IEEE} International Conference on Formal Methods and Models
               for System Design, {MEMOCODE} 2016, Kanpur, India, November 18-20,
               2016},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7786794},
  isbn      = {978-1-5090-2791-0},
  timestamp = {Thu, 05 Jan 2017 14:11:54 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/memocode/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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