BibTeX record conf/isvlsi/WilleSSD12

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@inproceedings{DBLP:conf/isvlsi/WilleSSD12,
  author       = {Robert Wille and
                  Mathias Soeken and
                  Eleonora Sch{\"{o}}nborn and
                  Rolf Drechsler},
  title        = {Circuit Line Minimization in the HDL-Based Synthesis of Reversible
                  Logic},
  booktitle    = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2012, Amherst,
                  MA, USA, August 19-21, 2012},
  pages        = {213--218},
  publisher    = {{IEEE} Computer Society},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISVLSI.2012.43},
  doi          = {10.1109/ISVLSI.2012.43},
  timestamp    = {Fri, 24 Mar 2023 00:02:41 +0100},
  biburl       = {https://dblp.org/rec/conf/isvlsi/WilleSSD12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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