BibTeX record conf/isvlsi/ChenLLJZCGLLWSC15

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@inproceedings{DBLP:conf/isvlsi/ChenLLJZCGLLWSC15,
  author       = {Xiaowen Chen and
                  Zhonghai Lu and
                  Yang Li and
                  Axel Jantsch and
                  Xueqian Zhao and
                  Shuming Chen and
                  Yang Guo and
                  Zonglin Liu and
                  Jianzhuang Lu and
                  Jianghua Wan and
                  Shuwei Sun and
                  Shenggang Chen and
                  Hu Chen},
  title        = {Achieving Memory Access Equalization Via Round-Trip Routing Latency
                  Prediction in 3D Many-Core NoCs},
  booktitle    = {2015 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2015,
                  Montpellier, France, July 8-10, 2015},
  pages        = {398--403},
  publisher    = {{IEEE} Computer Society},
  year         = {2015},
  url          = {https://doi.org/10.1109/ISVLSI.2015.8},
  doi          = {10.1109/ISVLSI.2015.8},
  timestamp    = {Fri, 24 Mar 2023 00:02:41 +0100},
  biburl       = {https://dblp.org/rec/conf/isvlsi/ChenLLJZCGLLWSC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}