BibTeX record conf/isscc/ClintonSTZSC18

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@inproceedings{DBLP:conf/isscc/ClintonSTZSC18,
  author       = {Michael Clinton and
                  Rajinder Singh and
                  Marty Tsai and
                  Shayan Zhang and
                  Bryan Sheffield and
                  Jonathan Chang},
  title        = {A 5GHz 7nm {L1} cache memory compiler for high-speed computing and
                  mobile applications},
  booktitle    = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2018, San Francisco, CA, USA, February 11-15, 2018},
  pages        = {200--201},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/ISSCC.2018.8310253},
  doi          = {10.1109/ISSCC.2018.8310253},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ClintonSTZSC18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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