BibTeX record conf/isscc/ClercSACDBBVZCS15

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@inproceedings{DBLP:conf/isscc/ClercSACDBBVZCS15,
  author       = {Sylvain Clerc and
                  Mehdi Saligane and
                  Fady Abouzeid and
                  Martin Cochet and
                  Jean{-}Marc Daveau and
                  Cyril Bottoni and
                  David Bol and
                  Julien De Vos and
                  Dominique Zamora and
                  Benjamin Coeffic and
                  Dimitri Soussan and
                  Damien Croain and
                  Mehdi Naceur and
                  Pierre Schamberger and
                  Philippe Roche and
                  Dennis Sylvester},
  title        = {8.4 {A} 0.33V/-40{\textdegree}C process/temperature closed-loop compensation
                  SoC embedding all-digital clock multiplier and {DC-DC} converter exploiting
                  {FDSOI} 28nm back-gate biasing},
  booktitle    = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2015, Digest of Technical Papers, San Francisco, CA, USA, February
                  22-26, 2015},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/ISSCC.2015.7062970},
  doi          = {10.1109/ISSCC.2015.7062970},
  timestamp    = {Sat, 09 Apr 2022 12:45:49 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ClercSACDBBVZCS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}