BibTeX record conf/isqed/VeeravalliSS14

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@inproceedings{DBLP:conf/isqed/VeeravalliSS14,
  author       = {Varadan Savulimedu Veeravalli and
                  Andreas Steininger and
                  Ulrich Schmid},
  title        = {Measuring {SET} pulsewidths in logic gates using digital infrastructure},
  booktitle    = {Fifteenth International Symposium on Quality Electronic Design, {ISQED}
                  2014, Santa Clara, CA, USA, March 3-5, 2014},
  pages        = {236--242},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISQED.2014.6783331},
  doi          = {10.1109/ISQED.2014.6783331},
  timestamp    = {Sat, 05 Sep 2020 18:01:43 +0200},
  biburl       = {https://dblp.org/rec/conf/isqed/VeeravalliSS14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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