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BibTeX record conf/async/MekieCSVT06
@inproceedings{DBLP:conf/async/MekieCSVT06, author = {Joycee Mekie and Supratik Chakraborty and Dinesh K. Sharma and Girish Venkataramani and P. S. Thiagarajan}, title = {Interface Design for Rationally Clocked {GALS} Systems}, booktitle = {12th {IEEE} International Symposium on Asynchronous Circuits and Systems {(ASYNC} 2006), 13-15 March 2006, Grenoble, France}, pages = {160--171}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/ASYNC.2006.19}, doi = {10.1109/ASYNC.2006.19}, timestamp = {Thu, 23 Mar 2023 23:58:24 +0100}, biburl = {https://dblp.org/rec/conf/async/MekieCSVT06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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