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Joseph Petolino

Joe Petolino

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Journal Articles

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1998
[j2]
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  dblp key:
  - journals/jssc/HealdSRKKLLP98
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  persistent URL:
  - https://dblp.org/rec/journals/jssc/HealdSRKKLLP98
Raymond A. Heald, Ken Shin, Vinita Reddy, I-Feng Kao, Masood Khan, William L. Lynch, Gary Lauterbach, Joe Petolino:
64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency. IEEE J. Solid State Circuits 33(11): 1682-1689 (1998)
1990
[j1]
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  - journals/micro/BrownACKMP90
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  - https://dblp.org/rec/journals/micro/BrownACKMP90
Emil W. Brown, Anant Agrawal, Trevor Creary, Michael F. Klein, Dave Murata, Joseph Petolino:
Implementing Sparc in ECL. IEEE Micro 10(1): 10-22 (1990)

Conference and Workshop Papers

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1994
[c2]
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  dblp key:
  - conf/itc/HoldbrookJMPRW94
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  - https://dblp.org/rec/conf/itc/HoldbrookJMPRW94
Kalon Holdbrook, Sunil Joshi, Samir Mitra, Joe Petolino, Renu Raman, Michelle Wong:
microSPARC^TM: A Case Study of Scan-Based Debug. ITC 1994: 70-75
1988
[c1]
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  - conf/compcon/AgrawalBPP88
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Anant Agrawal, Eric W. Brown, Joe Petolino, James R. Peterson:
Design Considerations for a Bipolar Implementation of SPARC. COMPCON 1988: 6-9

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