Keshavan Varadarajan

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Mythri Alle

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Publications

2011
[j2]
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Ratna Krishnamoorthy, Saptarsi Das, Keshavan Varadarajan, Mythri Alle, Masahiro Fujita, Soumitra Kumar Nandy, Ranjani Narayan:
Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture. IPSJ Trans. Syst. LSI Des. Methodol. 4: 193-209 (2011)
[c17]
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Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. ARC 2011: 125-132
2010
[c14]
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  - conf/cases/KrishnamoorthyVGANNF10
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Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita:
Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. CASES 2010: 77-86
[c13]
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  - conf/isvlsi/BiswasUMVANN10
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Prasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. ISVLSI 2010: 161-166
[c11]
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  - conf/samos/PrashankPDVANN10
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N. Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture. ICSAMOS 2010: 178-184
[c10]
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Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. ICSAMOS 2010: 265-272
2009
[j1]
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  - journals/tecs/AlleVFRNDBCRNN09
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Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan:
REDEFINE: Runtime reconfigurable polymorphic ASIC. ACM Trans. Embed. Comput. Syst. 9(2): 11:1-11:48 (2009)
[c9]
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Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan:
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. ARC 2009: 204-215
[c8]
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  - conf/cases/FellAVBDCNN09
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Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan:
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. CASES 2009: 127-136
2008
[c7]
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  - conf/asap/AlleVRNFRNN08
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Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan:
Synthesis of application accelerators on Runtime Reconfigurable Hardware. ASAP 2008: 13-18
[c6]
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Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan:
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. ASAP 2008: 251-256
[c5]
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  - conf/issoc/GargaAVNJ08
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Ganesh Garga, Mythri Alle, Keshavan Varadarajan, S. K. Nandy, H. S. Jamadagni:
Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network. SoC 2008: 1-4
2007
[c4]
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  - conf/fpl/SatrawalaVANN07
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A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. FPL 2007: 558-561

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