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Michael A. Riepe

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2000 – 2009

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2003
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Michael A. Riepe, Karem A. Sakallah:
Transistor placement for noncomplementary digital VLSI cell synthesis. ACM Trans. Design Autom. Electr. Syst. 8(1): 81-107 (2003)

1990 – 1999

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1999
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Michael A. Riepe, Karem A. Sakallah:
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis. ISPD 1999: 74-81
1998
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Michael A. Riepe, Karem A. Sakallah:
The edge-based design rule model revisited. ACM Trans. Design Autom. Electr. Syst. 3(3): 463-486 (1998)
1996
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Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown:
Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation. IEEE Trans. Very Large Scale Integr. Syst. 4(1): 113-129 (1996)
1993
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Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown:
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation. ICCD 1993: 361-364

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