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Journal Articles
- 2012
[j1]Felipe Frantz, Lioua Labrak, Ian O'Connor
:
3D IC floorplanning: Automating optimization settings and exploring new thermal-aware management techniques. Microelectron. J. 43(6): 423-432 (2012)
Conference and Workshop Papers
- 2024
- [c11]Alba Ordonez Rodriguez, Fabien Gilibert, Francois Paolini, Pascal Urard, Roberto Guizzetti, John Samuel, Remy Cellier, Lioua Labrak, Bastien Deveautour:
Artificial neural network-based solution for PSP MOSFET model card extraction. VLSID 2024: 6-12 - 2023
- [c10]Michel Chevalier, Severin Trochut, Roberto Guizzetti, Pascal Urard, Lioua Labrak, John Samuel, Remy Cellier, Nacer Abouchi:
Reinforcement Learning for Analog Sizing Optimization. SMACD 2023: 1-4 - 2020
- [c9]Adil Brik, Lioua Labrak, Ian O'Connor, Daniel Saias:
Fast hierarchical system synthesis based on predictive models. NEWCAS 2020: 70-73 - 2019
- [c8]Samuel Rigault, Nicolas Moeneclaey, Lioua Labrak, Ian O'Connor:
A Low-Voltage Sub-ns Pulse Integrated CMOS Laser Diode Driver for SPAD-based Time-of-Flight Rangefinding in Mobile Applications. SoCC 2019: 5-10 - [c7]Adil Brik, Lioua Labrak, Laurent Carrel, Ian O'Connor, Ramy Iskander:
Fast extraction of predictive models for integrated circuits using n-performance Pareto fronts. VLSI-SoC 2019: 281-286 - 2018
- [c6]Samuel Rigault, Nicolas Moeneclaey, Lioua Labrak, Ian O'Connor:
CMOS VCSEL driver dedicated for sub-nanosecond laser pulses generation in SPAD-based time-of-flight rangefinder. DCIS 2018: 1-6 - 2014
- [c5]Lioua Labrak, Ian O'Connor, Felipe Frantz:
Hierarchical design flow for heterogenous systems using Pareto front interpolation. ICECS 2014: 870-873 - 2012
- [c4]Firas Yengui, Lioua Labrak, Patrice Russo, Felipe Frantz, Nacer Abouchi:
Optimization based on surrogate modeling for analog integrated circuits. ICECS 2012: 9-12 - 2011
- [c3]Felipe Frantz, Lioua Labrak, Ian O'Connor:
3D-IC floorplanning: Applying meta-optimization to improve performance. VLSI-SoC 2011: 404-409 - 2010
- [c2]Bo Wang, Ian O'Connor, Emmanuel Drouard, Lioua Labrak:
Bottom-up Verification Methodology for CMOS Photonic Linear Heterogeneous System. FDL 2010: 149-154 - 2007
- [c1]Lioua Labrak, T. Tixier, Y. Fellah, Nacer Abouchi:
Automated cost function formulation for analog design optimization. ECCTD 2007: 559-562
Coauthor Index
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