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ORCIDDoru-Florin Chiper
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Journal Articles
- 2023
[j13]Doru-Florin Chiper
, Arcadie Cracan:
New Systolic Array Algorithms and VLSI Architectures for 1-D MDST. Sensors 23(13): 6220 (2023)- [j12]Radu Matei, Doru-Florin Chiper:
Analytic Design Technique for 2D FIR Circular Filter Banks and Their Efficient Implementation Using Polyphase Approach. Sensors 23(24): 9851 (2023) - [j11]Ahcen Aliouat, Nasreddine Kouadria, Doru-Florin Chiper:
x-DTT: A package for calculating real and Integer Discrete Tchebichef Transform kernels based on orthogonal polynomials. SoftwareX 23: 101441 (2023) - 2021
- [j10]Doru-Florin Chiper:
A Structured Fast Algorithm for the VLSI Pipeline Implementation of Inverse Discrete Cosine Transform. Circuits Syst. Signal Process. 40(11): 5351-5366 (2021) - 2018
- [j9]Doru-Florin Chiper:
A Structured Dual Split-Radix Algorithm for the Discrete Hartley Transform of Length \(2^{N}\). Circuits Syst. Signal Process. 37(1): 290-304 (2018) - 2013
- [j8]Doru-Florin Chiper:
A Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecture. IEEE Trans. Circuits Syst. II Express Briefs 60-II(5): 282-286 (2013) - 2012
- [j7]Doru-Florin Chiper:
Radix-2 Fast Algorithm for Computing Discrete Hartley Transform of Type III. IEEE Trans. Circuits Syst. II Express Briefs 59-II(5): 297-301 (2012) - 2011
- [j6]Doru-Florin Chiper:
A new VLSI algorithm and architecture for the hardware implementation of type IV discrete cosine transform using a pseudo-band correlation structure. Central Eur. J. Comput. Sci. 1(2): 243-250 (2011) - [j5]Doru-Florin Chiper, Paul Ungureanu:
Novel VLSI Algorithm and Architecture with Good Quantization Properties for a High-Throughput Area Efficient Systolic Array Implementation of DCT. EURASIP J. Adv. Signal Process. 2011 (2011) - [j4]Doru-Florin Chiper:
Fast Radix-2 Algorithm for the Discrete Hartley Transform of Type II. IEEE Signal Process. Lett. 18(11): 687-689 (2011) - 2007
- [j3]Doru-Florin Chiper, M. N. S. Swamy, M. Omair Ahmad:
An Efficient Unified Framework for Implementation of a Prime-Length DCT/IDCT With High Throughput. IEEE Trans. Signal Process. 55(6-2): 2925-2936 (2007) - 2005
- [j2]Doru-Florin Chiper, M. N. Shanmukha Swamy, M. Omair Ahmad, Thanos Stouraitis:
Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(6): 1125-1137 (2005) - 2002
- [j1]Doru-Florin Chiper, M. N. S. Swamy, M. Omair Ahmad, Thanos Stouraitis:
A systolic array architecture for the discrete sine transform. IEEE Trans. Signal Process. 50(9): 2347-2354 (2002)
Conference and Workshop Papers
- 2023
- [c11]Doru-Florin Chiper, Radu Matei:
Polyphase Implementation for Gaussian 2D FIR Filters with Circular Symmetry. ECAI 2023: 1-6 - 2022
- [c10]Doru-Florin Chiper, Laura-Teodora Cotorobai:
An Improved Algorithm for an Efficient VLSI Implementation of Type IV DST using Short Quasi-Band Correlation Structures. ECAI 2022: 1-4 - [c9]Doru-Florin Chiper, Arcadie Cracan:
A New Integer Algorithm for a VLSI Implementation of DCT Using Obfuscation Technique. COMM 2022: 1-4 - [c8]Doru-Florin Chiper:
An Improved Algorithm for the VLSI Implementation of Type II Generalized DHT that Allows an Efficient Incorporation of Obfuscation Technique. TSP 2022: 83-86 - 2020
- [c7]Doru-Florin Chiper, Laura-Teodora Cotorobai:
A New VLSI Algorithm for an Efficient VLSI Implementation of Type IV DST based on Short Band- Correlation Structures. COMM 2020: 69-72 - [c6]Laura-Teodora Cotorobai, Doru-Florin Chiper:
A New VLSI Algorithm for type IV DCT for an Efficient Implementation of Obfuscation Technique. TSP 2020: 519-522 - 2018
- [c5]Doru-Florin Chiper, Laura-Teodora Cotorobai:
A Unified VLSI architecture for 1D IDCT and IDST based on pseudo-band correlations. ECAI 2018: 1-5 - 2016
- [c4]Doru-Florin Chiper:
A new VLSI algorithm for a high-throughput implementation of type IV DCT. COMM 2016: 17-20 - 2008
- [c3]Doru-Florin Chiper, M. N. S. Swamy, M. Omair Ahmad:
A new systolic array algorithm for a high throughput low cost VLSI implementation of DCT. ICECS 2008: 490-493 - 1999
- [c2]Doru-Florin Chiper:
A Systolic Array Algorithm for an Efficient Unified Memory-Based Implementation of the Inverse Discrete Cosine and Sine Transforms. ICIP (2) 1999: 764-768 - 1997
- [c1]Doru-Florin Chiper:
A new systolic array algorithm for memory-based VLSI array implementation of DCT. ISCC 1997: 297-301
Coauthor Index
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