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2020 – today
- 2024
[j7]Yu-Lun Hsu
, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang:
GC-Like LDPC Code Construction and its NN-Aided Decoder Implementation. IEEE Open J. Circuits Syst. 5: 189-198 (2024)- 2023
- [c21]Xiao-Juan Huang, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang, Sau-Gee Chen:
A MATE-GDBF Algorithm for Irregular Punctured LDPC Codes and Its Decoder Implementation. APCCAS 2023: 323-327 - 2022
- [j6]Li-Wei Liu, Mu-Hua Yuan, Yen-Chin Liao, Hsie-Chia Chang:
A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories. IEEE Open J. Circuits Syst. 3: 180-191 (2022) - [j5]Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang:
UP-GDBF: A 19.3 Gbps Error Floor Free 4KB LDPC Decoder for NAND Flash Applications. IEEE Open J. Circuits Syst. 3: 228-236 (2022) - [c20]Shao Wen Cheng, Kai Jyun Hung, Hsie-Chia Chang, Yen-Chin Liao:
An Attention-based Neural Network on Multiple Speaker Diarization. AICAS 2022: 431-434 - [c19]Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang:
A Clustering-based ML Scheme for Capacity Approaching Soft Level Sensing in 3D TLC NAND. ICASSP 2022: 4078-4082 - 2021
- [c18]Chieh-Yu Lin, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang:
A 33.2 Gbps/Iter. Reconfigurable LDPC Decoder Fully Compliant with 5G NR Applications. ISCAS 2021: 1-5 - [c17]Yu-En Hsu, Yen-Chin Liao, Hsie-Chia Chang:
A Two-Stage Path Planning Engine for Robot Navigation System. SoCC 2021: 218-223 - 2020
- [c16]Yi-An Chen, Gung-Yu Pan, Che-Hua Shih, Yen-Chin Liao, Chia-Chih Yen, Hsie-Chia Chang:
Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification. DATE 2020: 891-896
2010 – 2019
- 2019
- [j4]Yen-Chin Liao, Chien Lin, Hsie-Chia Chang, Shu Lin:
A (21150, 19050) GC-LDPC Decoder for NAND Flash Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1219-1230 (2019) - [c15]Wei-Chien Kuo, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang:
ML-based Thermal Sensor Calibration by Bivariate Gaussian Mixture Model Estimation. SoCC 2019: 113-117 - 2018
- [c14]Po-Hsun Chang, Chen-Yang Lin, Chia-Hsiang Sun, Yen-Chin Liao, Hsie-Chia Chang:
A 188-Length Full Code Rate 333Mbps 1.08mm2 Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A. ISCAS 2018: 1-4 - [c13]Yen-Chin Liao, Hsie-Chia Chang, Shu Lin:
Scalable Globally-Coupled Low-Density Parity Check Codes. ISTC 2018: 1-5 - [c12]Yen-Chin Liao, Hsie-Chia Chang, Shu Lin:
Generalized Globally-Coupled Low-Density Parity-Check Codes. ITW 2018: 1-5 - [c11]Fang-Ju Ku, Tung-Yu Wu, Yen-Chin Liao, Hsie-Chia Chang, Wing Hung Wong, Chen-Yi Lee:
A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. VLSI-DAT 2018: 1-4 - 2015
- [c10]Kin-Chu Ho, Chih-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang, Chen-Yi Lee:
A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. ISCAS 2015: 1450-1453 - [c9]Kuo-Kuang Yen, Yen-Chin Liao, Hsie-Chia Chang:
Design of LT code degree distribution with profiled output ripple size. SiPS 2015: 1-6 - 2013
- [j3]Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang:
Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes. IEEE Commun. Lett. 17(5): 976-979 (2013) - [j2]Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, John K. Zao, Hsie-Chia Chang:
Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection. IEEE Trans. Multim. 15(8): 2162-2175 (2013) - [c8]Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang:
Adjusted robust Soliton distribution (ARSD) with reshaped ripple size for LT codes. WCSP 2013: 1-6 - 2012
- [c7]Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang:
Non-repetitive encoding with increased degree-1 encoding symbols for LT codes. APCCAS 2012: 655-658
2000 – 2009
- 2008
- [c6]Yi Hsuan Wu, Yu Ting Liu, Hsiu-Chi Chang, Yen-Chin Liao, Hsie-Chia Chang:
Early-Pruned K-Best Sphere Decoding Algorithm Based on Radius Constraints. ICC 2008: 4496-4500 - [c5]Yi-Kai Lin, Chin-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang:
Structured LDPCcodes with low error floor based on PEG tanner graphs. ISCAS 2008: 1846-1849 - 2007
- [j1]Yen-Chin Liao, Chien-Ching Lin, Hsie-Chia Chang, Chih-Wei Liu:
Self-Compensation Technique for Simplified Belief-Propagation Algorithm. IEEE Trans. Signal Process. 55(6-2): 3061-3072 (2007) - [c4]Hsiu-Chi Chang, Yen-Chin Liao, Hsie-Chia Chang:
Low-complexity Prediction Techniques of K-best Sphere Decoding for MIMO Systems. SiPS 2007: 45-49 - 2006
- [c3]Hong-An Huang, Yen-Chin Liao, Hsie-Chia Chang:
A self-compensation fixed-width booth multiplier and its 128-point FFT applications. ISCAS 2006 - [c2]Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu:
Carry Estimation for Two's Complement Fixed-Width Multipliers. SiPS 2006: 345-350 - 2004
- [c1]Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen:
Static floating-point unit with implicit exponent tracking for embedded DSP. ISCAS (2) 2004: 821-824
Coauthor Index
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