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Rohini Krishnan
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Conference and Workshop Papers
- 2023
- [c9]Rohini Krishnan, Tejas P. Potphode, Ashish Sharma, Haijin Zhang, Herry Hu, David R. Mulvihill:
Design techniques for reference clock jitter optimization for high speed PHYs. DTTIS 2023: 1-6 - 2006
- [c8]Maurice Meijer, Rohini Krishnan, Martijn T. Bennebroek:
Energy-efficient FPGA interconnect design. DATE Designers' Forum 2006: 42-47 - 2005
- [c7]Rohini Krishnan, R. I. M. P. Meijer, Durand Guillaume:
Energy-efficient FPGA interconnect architecture design (abstract only). FPGA 2005: 268 - 2004
- [c6]Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek:
Low energy FPGA interconnect design. FPGA 2004: 255 - [c5]Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek:
Low energy FPGA interconnect design. ACM Great Lakes Symposium on VLSI 2004: 393-396 - [c4]Rohini Krishnan, José Pineda de Gyvez:
Low Energy Switch Block For FPGAs. VLSI Design 2004: 209-214 - 2003
- [c3]Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick:
Encoded-Low Swing Technique for Ultra Low Power Interconnect. FPL 2003: 240-251 - [c2]Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar:
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks. VLSI Design 2003: 177-182 - 2002
- [c1]Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan:
A New Divide and Conquer Method for Achieving High Speed Division in Hardware. ASP-DAC/VLSI Design 2002: 535-540
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