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ORCIDVu Manh Tuan
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2000 – 2009
- 2009
[c8]Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano:
Evaluation of a multicore reconfigurable architecture with variable core sizes. IPDPS 2009: 1-8- 2008
- [j2]Vu Manh Tuan, Hideharu Amano:
A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors. IEICE Trans. Inf. Syst. 91-D(9): 2312-2322 (2008) - [j1]Vu Manh Tuan, Hideharu Amano:
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors. IEICE Trans. Inf. Syst. 91-D(12): 2793-2803 (2008) - [c7]Vu Manh Tuan, Hideharu Amano:
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor. ARC 2008: 171-182 - [c6]Vu Manh Tuan, Hideharu Amano:
A Method for Capturing State Data on Dynamically Reconfigurable Processors. ERSA 2008: 208-214 - 2007
- [c5]Vu Manh Tuan, Yohei Hasegawa, Hideharu Amano:
Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor. ERSA 2007: 203-206 - [c4]Vu Manh Tuan, Hideharu Amano:
A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors. FPT 2007: 357-360 - 2006
- [c3]Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano:
Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor. ARC 2006: 115-121 - [c2]Yohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, Takuro Nakamura, Takashi Nishimura, Hideharu Amano:
Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. IPDPS 2006 - [c1]Masayasu Suzuki, Yohei Hasegawa, Vu Manh Tuan, Shohei Abe, Hideharu Amano:
A cost-effective context memory structure for dynamically reconfigurable processors. IPDPS 2006
Coauthor Index
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