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Jean Paul Caisso

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1990 – 1999

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1991
[j1]
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Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin:
A recursive technique for computing delays in series-parallel MOS transistor circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5): 589-595 (1991)

1980 – 1989

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1988
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Jean Paul Caisso, Bernard Courtois:
Fault Simulation and Test Pattern Generation at the Multiple-Valued Switch Level. ITC 1988: 94-101
1987
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Jean Paul Caisso:
Contribution à la vérification des circuits intégrés dans un environnement multivalué. (Contribution to the verification of integrated circuits in a multivalued environment). Grenoble Institute of Technology, France, 1987

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