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ORCIDRangharajan Venkatesan
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2020 – today
- 2024
[c31]Kavya Sreedhar, Jason Clemons, Rangharajan Venkatesan, Stephen W. Keckler, Mark Horowitz:
Vision Transformer Computation and Resilience for Dynamic Inference. ISPASS 2024: 192-204- 2023
- [j12]Ben Keller
, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, Charbel Sakr, William J. Dally, C. Thomas Gray, Brucek Khailany:
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm. IEEE J. Solid State Circuits 58(4): 1129-1141 (2023) - [c30]Steve Dai, Hasan Genc, Rangharajan Venkatesan, Brucek Khailany:
Efficient Transformer Inference with Statically Structured Sparse Attention. DAC 2023: 1-6 - 2022
- [j11]Geoffrey W. Burr, Sukhwan Lim, Boris Murmann, Rangharajan Venkatesan, Marian Verhelst:
Fair and Comprehensive Benchmarking of Machine Learning Processing Chips. IEEE Des. Test 39(3): 18-27 (2022) - [j10]Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Fayez Ali, Ming-Yu Liu, Brucek Khailany, William J. Dally, Anima Anandkumar:
LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update. IEEE Trans. Computers 71(12): 3179-3190 (2022) - [c29]Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany:
Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. ICML 2022: 19123-19138 - [c28]Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, William J. Dally, C. Thomas Gray, Brucek Khailany:
A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. VLSI Technology and Circuits 2022: 16-17 - [i7]Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany:
Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. CoRR abs/2206.06501 (2022) - [i6]Kavya Sreedhar, Jason Clemons, Rangharajan Venkatesan, Stephen W. Keckler, Mark Horowitz:
Enabling and Accelerating Dynamic Vision Transformer Inference for Real-Time Applications. CoRR abs/2212.02687 (2022) - 2021
- [j9]Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler:
Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM 64(6): 107-116 (2021) - [c27]Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan:
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. DAC 2021: 469-474 - [c26]Nathaniel Ross Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany:
IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs. ICCAD 2021: 1-9 - [c25]Thomas Burd, Rangharajan Venkatesan, Dennis Sylvester:
Session 3 Overview: Highlighted Chip Releases: Modern Digital SoCs Invited Papers. ISSCC 2021: 44-45 - [c24]Steve Dai, Rangharajan Venkatesan, Mark Ren, Brian Zimmer, William J. Dally, Brucek Khailany:
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. MLSys 2021 - [i5]Steve Dai, Rangharajan Venkatesan, Haoxing Ren, Brian Zimmer, William J. Dally, Brucek Khailany:
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. CoRR abs/2102.04503 (2021) - [i4]Steve Dai, Alicia Klinefelter, Haoxing Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Ross Pinckney, Brucek Khailany:
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking. CoRR abs/2102.06326 (2021) - [i3]Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan:
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. CoRR abs/2103.09301 (2021) - [i2]Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Ming-Yu Liu, Brucek Khailany, Bill Dally, Anima Anandkumar:
Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update. CoRR abs/2106.13914 (2021) - 2020
- [j8]Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany:
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits 55(4): 920-932 (2020) - [j7]Brucek Khailany, Haoxing Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William J. Dally:
Accelerating Chip Design With Machine Learning. IEEE Micro 40(6): 23-32 (2020)
2010 – 2019
- 2019
- [c23]Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Clayton Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel S. Emer:
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration. ASPLOS 2019: 137-151 - [c22]Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Ningxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William J. Dally, C. Thomas Gray:
Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference. DAC 2019: 81 - [c21]Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany:
A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium 2019: 1-24 - [c20]Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany:
MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD 2019: 1-8 - [c19]Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel S. Emer:
Timeloop: A Systematic Approach to DNN Accelerator Evaluation. ISPASS 2019: 304-315 - [c18]Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler:
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO 2019: 14-27 - [c17]Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany:
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits 2019: 300- - 2018
- [c16]Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer:
A modular digital VLSI flow for high-productivity SoC design. DAC 2018: 72:1-72:6 - 2017
- [c15]Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan:
STAxCache: An approximate, energy efficient STT-MRAM cache. DATE 2017: 356-361 - [c14]Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally:
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. ISCA 2017: 27-40 - [i1]Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally:
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. CoRR abs/1708.04485 (2017) - 2016
- [j6]A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy:
Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes. ACM J. Emerg. Technol. Comput. Syst. 13(2): 23:1-23:22 (2016) - [j5]Xuanyao Fong, Yusung Kim, Rangharajan Venkatesan, Sri Harsha Choday, Anand Raghunathan, Kaushik Roy:
Spin-Transfer Torque Memories: Devices, Circuits, and Systems. Proc. IEEE 104(7): 1449-1488 (2016) - [j4]Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Mrigank Sharad, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan:
Cache Design with Domain Wall Memory. IEEE Trans. Computers 65(4): 1010-1024 (2016) - [j3]Xuanyao Fong, Rangharajan Venkatesan, Dongsoo Lee, Anand Raghunathan, Kaushik Roy:
Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 992-1002 (2016) - [j2]Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey:
Emulation-Based Analysis of System-on-Chip Performance Under Variations. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3401-3414 (2016) - [c13]Injoon Hong, Jason Clemons, Rangharajan Venkatesan, Iuri Frosio, Brucek Khailany, Stephen W. Keckler:
A real-time energy-efficient superpixel hardware accelerator for mobile computer vision applications. DAC 2016: 95:1-95:6 - 2015
- [j1]Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan:
Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage. ACM J. Emerg. Technol. Comput. Syst. 12(1): 4:1-4:27 (2015) - [c12]Ashish Ranjan, Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Vijay S. Pai, Kaushik Roy, Anand Raghunathan:
DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>s. DATE 2015: 181-186 - [c11]A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy:
Asymmetric underlapped FinFET based robust SRAM design at 7nm node. DATE 2015: 659-664 - [c10]Rangharajan Venkatesan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan:
Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computing. DATE 2015: 1575-1578 - 2014
- [b1]Rangharajan Venkatesan:
Computing with Spintronics: Circuits and architectures. Purdue University, USA, 2014 - [c9]Rangharajan Venkatesan, Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies. ISCA 2014: 253-264 - [c8]Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan:
SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing. ISLPED 2014: 15-20 - 2013
- [c7]Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan:
DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes. DATE 2013: 1825-1830 - [c6]Mrigank Sharad, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy:
Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches. ISLPED 2013: 64-69 - [c5]Mrigank Sharad, Rangharajan Venkatesan, Xuanyao Fong, Anand Raghunathan, Kaushik Roy:
Reading spin-torque memory with spin-torque sensors. NANOARCH 2013: 40-41 - 2012
- [c4]Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan:
TapeCache: a high density, energy efficient cache based on domain wall memory. ISLPED 2012: 185-190 - 2011
- [c3]Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey:
VESPA: Variability emulation for System-on-Chip performance analysis. DATE 2011: 2-7 - [c2]Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan:
MACACO: Modeling and analysis of circuits for approximate computing. ICCAD 2011: 667-673 - [c1]Rangharajan Venkatesan, Vinay K. Chippa, Charles Augustine, Kaushik Roy, Anand Raghunathan:
Energy efficient many-core processor for recognition and mining using spin-based memory. NANOARCH 2011: 122-128
Coauthor Index
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