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Jaswanth Sreeram
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2010 – 2019
- 2017
- [c13]Cosmin Radoi, Stephan Herhut, Jaswanth Sreeram, Danny Dig:
Are Web Applications Ready for Parallelism? HICSS 2017: 1-10 - 2015
- [c12]Cosmin Radoi, Stephan Herhut, Jaswanth Sreeram, Danny Dig:
Are web applications ready for parallelism? PPoPP 2015: 289-290 - 2013
- [c11]Stephan Herhut, Richard L. Hudson, Tatiana Shpeisman, Jaswanth Sreeram:
River trail: a path to parallelism in JavaScript. OOPSLA 2013: 729-744 - [c10]Stephan Herhut, Richard L. Hudson, Tatiana Shpeisman, Jaswanth Sreeram:
Parallel JavaScript: bringing the compute power of multi-core CPUs and GPUs to the world of web graphics. SIGGRAPH Talks 2013: 45:1 - 2012
- [c9]Stephan Herhut, Richard L. Hudson, Tatiana Shpeisman, Jaswanth Sreeram:
Parallel Programming for the Web. HotPar 2012 - [c8]Jaswanth Sreeram, Santosh Pande:
Hybrid Transactions: Lock Allocation and Assignment for Irrevocability. IPDPS 2012: 1192-1203 - [c7]Jaswanth Sreeram, Santosh Pande:
Safe compiler-driven transaction checkpointing and recovery. OOPSLA 2012: 41-56 - 2011
- [b1]Jaswanth Sreeram:
Optimistic semantic synchronization. Georgia Institute of Technology, Atlanta, GA, USA, 2011 - [c6]Jaswanth Sreeram, Santosh Pande:
Parallelizing a Real-Time Physics Engine Using Transactional Memory. Euro-Par (2) 2011: 206-223 - [c5]Romain Cledat, Tushar Kumar, Jaswanth Sreeram, Santosh Pande:
Enriching 3-D Video Games on Multicores. IPDPS 2011: 176-187 - 2010
- [c4]Jaswanth Sreeram, Santosh Pande:
Exploiting approximate value locality for data synchronization on multi-core processors. IISWC 2010: 1-10
2000 – 2009
- 2008
- [c3]Tushar Kumar, Romain Cledat, Jaswanth Sreeram, Santosh Pande:
Statistically Analyzing Execution Variance for Soft Real-Time Applications. LCPC 2008: 124-140 - 2007
- [c2]Jaswanth Sreeram, Romain Cledat, Tushar Kumar, Santosh Pande:
RSTM : A Relaxed Consistency Software Transactional Memory for Multicores. PACT 2007: 428 - [c1]Tushar Kumar, Jaswanth Sreeram, Romain Cledat, Santosh Pande:
A profile-driven statistical analysis framework for the design optimization of soft real-time applications. ESEC/SIGSOFT FSE 2007: 529-532 - 2006
- [j1]Subramanian Ramaswamy, Jaswanth Sreeram, Sudhakar Yalamanchili, Krishna V. Palem:
Data trace cache: an application specific cache architecture. SIGARCH Comput. Archit. News 34(1): 11-18 (2006)
Coauthor Index
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