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ORCIDCan Wang 0009
Person information
- affiliation: Stanford University, CA, USA
- affiliation: Hong Kong University of Science and Technology, HKUST, Optical Wireless Laboratory, IC Design Center, Department of Electronic and Computer Engineering, Kowloon, Hong Kong
- affiliation (2017): Fudan University, PhotonIC Technologies, State Key Laboratory of ASIC and System, Shanghai, China
Other persons with the same name
- Can Wang — disambiguation page
- Can Wang 0001
![[0000-0002-5890-4307]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-5890-4307")
— Zhejiang University, College of Computer Science, Zhejiang Provincial Key Laboratory of Service Robot, Hangzhou, China - Can Wang 0002 — Chinese Academy of Sciences, Shenzhen Institutes of Advanced Technology, Guangdong Provincial Key Laboratory of Robotics and Intelligent System, China (and 2 more)
- Can Wang 0003 — Harbin Institute of Technology, State Key Laboratory of Robotics and System, China
- Can Wang 0004 — Griffith University, Australia (and 2 more)
- Can Wang 0006 — Peking University, Shenzhen Graduate School, Key Laboratory of Machine Perception, Beijing, China
- Can Wang 0007 — City University of Hong Kong, Department of Computer Science, Chow Yei Ching School of Graduate Studies, Hong Kong (and 1 more)
- Can Wang 0008 — China Three Gorges University, College of Electrical Engineering and New Energy, Yichang, China (and 1 more)
- Can Wang 0010 — Shenzhen University, College of Mechatronics and Control Engineering, China (and 1 more)
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2020 – today
- 2024
[j4]Li Wang, Zhao Zhang, Can Wang, Rehan Azmat, Weimin Shi, C. Patrick Yue:
A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR. IEEE J. Solid State Circuits 59(2): 449-463 (2024)- 2021
- [j3]Can Wang, Li Wang, Zhao Zhang, Milad Kalantari Mahmoudabadi, Weimin Shi, C. Patrick Yue:
A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. IEEE Open J. Circuits Syst. 2: 46-55 (2021) - [j2]Rehan Azmat, Li Wang, Khawaja Qasim Maqbool, Can Wang, C. Patrick Yue:
Sensing and Cancellation Circuits for Mitigating EMI-Related Common Mode Noise in High-Speed PAM-4 Transmitter. IEEE Trans. Circuits Syst. I Regul. Pap. 68(11): 4545-4555 (2021) - 2020
- [j1]Zhao Zhang, Guang Zhu, Can Wang, Li Wang, C. Patrick Yue:
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator. IEEE J. Solid State Circuits 55(10): 2734-2746 (2020) - [c4]Jian Kang, Xuanzheng Wang, Li Wang, Can Wang, C. Patrick Yue:
A Real-Time RGB PAM-4 Visible Light Communication System Based on a Transceiver Design with Pre- and Post-equalizations. MLICOM 2020: 265-270
2010 – 2019
- 2019
- [c3]Zhao Zhang, Guang Zhu, Can Wang, Li Wang, C. Patrick Yue:
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator. A-SSCC 2019: 241-242 - [c2]Can Wang, Guang Zhu, Zhao Zhang, C. Patrick Yue:
A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. VLSI Circuits 2019: 274- - 2018
- [c1]Xiangyu Meng, Can Wang, Milad Kalantari, C. Patrick Yue:
A 16-GB/S 0-DB Power Back-Off 16-QAM Transmitter at 28 GHZ in 65-NM CMOS. VLSI Circuits 2018: 217-218
Coauthor Index
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last updated on 2024-06-13 23:25 CEST by the dblp team
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