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2020 – today
- 2020
[j4]Yasin Oge, Yuta Kobayashi, Takahiro Yamaura, Tomonori Maegawa:
Software-Based Time-Aware Shaper for Time-Sensitive Networks. IEICE Trans. Commun. 103-B(3): 167-180 (2020)
2010 – 2019
- 2017
- [j3]Masato Yoshimi
, Yasin Oge, Tsutomu Yoshinaga:
Pipelined Parallel Join and Its FPGA-Based Acceleration. ACM Trans. Reconfigurable Technol. Syst. 10(4): 28:1-28:28 (2017) - 2015
- [j2]Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga:
Design and Evaluation of a Configurable Query Processing Hardware for Data Streams. IEICE Trans. Inf. Syst. 98-D(12): 2207-2217 (2015) - 2014
- [c6]Masato Yoshimi, Ryu Kudo, Yasin Oge, Yuta Terada, Hidetsugu Irie, Tsutomu Yoshinaga:
Accelerating OLAP Workload on Interconnected FPGAs with Flash Storage. CANDAR 2014: 440-446 - [c5]Masato Yoshimi, Ryu Kudo, Yasin Oge, Yuta Terada, Hidetsugu Irie, Tsutomu Yoshinaga:
An FPGA-Based Tightly Coupled Accelerator for Data-Intensive Applications. MCSoC 2014: 289-296 - 2013
- [c4]Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga:
An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGA. CANDAR 2013: 112-121 - [c3]Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga:
A fast handshake join implementation on FPGA with adaptive merging network. SSDBM 2013: 44:1-44:4 - 2012
- [j1]Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga:
Design and Implementation of a Handshake Join Architecture on FPGA. IEICE Trans. Inf. Syst. 95-D(12): 2919-2927 (2012) - [c2]Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga:
Design and Implementation of a Merging Network Architecture for Handshake Join Operator on FPGA. MCSoC 2012: 84-91 - 2011
- [c1]Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga:
An Implementation of Handshake Join on FPGA. ICNC 2011: 95-104
Coauthor Index
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