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ORCIDShigeya Tanaka
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1990 – 1999
- 1998
[j5]Shoji Yoshida, Shigeya Tanaka, Kotaro Matsuo, Takashi Hotta, Hideo Sawamoto, Teruhisa Shimizu:
Instruction fetch and dispatch scheme with flag-in-cache/in-IBR. Syst. Comput. Jpn. 29(4): 86-94 (1998)- 1996
- [j4]Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Takahiro Nishiyama, Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, Teruhisa Shimizu, Hideo Sawamoto:
2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor. IEEE J. Solid State Circuits 31(7): 972-980 (1996) - 1995
- [c2]Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa:
A superscalar RISC processor with pseudo vector processing feature. ICCD 1995: 102-109 - 1994
- [j3]Fumio Murabayashi, Takashi Hotta, Shigeya Tanaka, Tatsumi Yamauchi, Hiromichi Yamada, Tetsuo Nakano, Yutaka Kobayashi, Tadaaki Bandoh:
3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. IEEE J. Solid State Circuits 29(3): 298-302 (1994) - [j2]Shigeya Tanaka, Takashi Hotta, Fumio Murabayashi, Hiromichi Yamada, Shoji Yoshida, Kotaro Shimamura, Koyo Katsura, Tadaaki Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, Tetsuo Nakano, Teruhisa Shimizu, Ryuichi Satomura:
A 120-MHz BiCMOS superscalar RISC processor. IEEE J. Solid State Circuits 29(4): 389-396 (1994)
1980 – 1989
- 1989
- [c1]Yasuhiro Nakatsuka, Takashi Hotta, Shigeya Tanaka, Tadaaki Bandoh, Ryuichi Satomura, Syuichi Nakagami, Tetsuo Nakano, Atsuo Hotta, Takashi Moriyama, Shigemi Adachi, Shoji Iwamoto:
A high performance BiCMOS 32-bit microprocessor. ICCD 1989: 358-361 - 1988
- [j1]Takashi Hotta, Kouzaburou Kurita, Hideo Maejima, Masahiro Iwamura, Shigeya Tanaka, Tadaaki Bandoh, Tatsumi Yamauchi, Atsuo Hotta:
1.3- mu m CMOS/bipolar standard cell library for VLSI computers. IEEE J. Solid State Circuits 23(2): 500-506 (1988)
Coauthor Index
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