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Marius Evers
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Books and Theses
- 2000
- [b1]Marius Evers:
Improving branch prediction by understanding branch behavior. University of Michigan, USA, 2000
Journal Articles
- 2001
- [j4]Marius Evers, Tse-Yu Yeh:
Understanding branches and designing branch predictors for high-performance microprocessors. Proc. IEEE 89(11): 1610-1620 (2001) - 1998
- [j3]Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt:
Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures. Int. J. Parallel Program. 26(4): 449-478 (1998) - 1997
- [j2]Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark:
One Billion Transistors, One Uniprocessor, One Chip. Computer 30(9): 51-57 (1997) - [j1]Po-Yung Chang, Marius Evers, Yale N. Patt:
Improving branch prediction accuracy by reducing pattern history table interference. Int. J. Parallel Program. 25(5): 339-362 (1997)
Conference and Workshop Papers
- 2007
- [c7]Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari:
Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. ISPD 2007: 67-74 - 1998
- [c6]Jared Stark, Marius Evers, Yale N. Patt:
Variable Length Path Branch Prediction. ASPLOS 1998: 170-179 - [c5]Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt:
An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. ISCA 1998: 52-61 - [c4]Sanjay J. Patel, Marius Evers, Yale N. Patt:
Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. ISCA 1998: 262-271 - 1996
- [c3]Po-Yung Chang, Marius Evers, Yale N. Patt:
Improving branch prediction accuracy by reducing pattern history table interference. IEEE PACT 1996: 48-57 - [c2]Marius Evers, Po-Yung Chang, Yale N. Patt:
Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. ISCA 1996: 3-11 - [c1]Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt:
Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures. MICRO 1996: 191-200
Coauthor Index
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